The present invention relates to a method of making a MIS (Metal Insulator Semiconductor) FET (Field Effect Transistor) of a miniature structure with reduced hot carrier effect.
To increase the degree of integration, the size of the MIS FET must be reduced. When the channel length of a MIS FET is reduced, the electric field proximate to the drain is intensified and hot carriers are generated. The hot carriers can be injected into the gate dielectric film deteriorating the device characteristics. To alleviate the intensity of the electric field, the LDD (Lightly Doped Drain) structure is employed.
An example of the LDD structure is disclosed in the IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April 1982, pp. 590-596, "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", Tsang, et al. This LDDFET is described with reference to FIGS. 1A to 1F.
As illustrated in FIG. 1A, a silicon substrate 1 is prepared, on which a field oxide film 2, a gate oxide film 3, a polycrystalline silicon (poly-Si) film 4 and a CVD SiO.sub.2 film 5 (SiO.sub.2 film formed by chemical vapor deposition) are formed in turn.
Next, as illustrated in FIG. 1B, the CVD SiO.sub.2 film 5 and the poly-Si film 4 are pattterned. The patterned poly-Si film 4 constitutes a gate electrode.
Next, as illustrated in FIG. 1C, ion-implantation is performed using the patterned films 5 and 4 as a mask (i.e., by self-alignment) to form N-regions (lightly-doped regions) 6 in the silicon substrate 1.
Next, as illustrated in FIG. 1D, a CVD SiO.sub.2 film 7 is deposited over the entire surface.
Next, as illustrated in FIG. 1E, RIE (reactive ion etching) is performed to form sidewalls 8.
Next, as illustrated in FIG. 1F, ion-implantation is performed using the patterned films 5 and 4, and the sidewalls 8 as a mask (i.e., by self-alignment) to form N.sup.+ regions (heavily-doped regions) 9.
Subsequently, and interlayer insulating film is deposited, and a contact is opened and an Al (aluminum) conductor layer 10 is formed to obtain an LDDFET as shown in FIG. 2.
In this way, the lightly-doped regions are formed under the sidewalls 8 to alleviate the electric field intensity.
The above-described conventional LDD structure has a problem in that if the N.sup.- region is formed to minimize the electric field near the drain, the impurity concentration of the N.sup.- region is on the order of 10.sup.17 cm.sup.-3, so that the parasitic resistance between the source and the drain is increased and the conductance is descreased, Moreover, when a negative change is trapped in the oxide film over the N.sup.- region, the N.sup.- region is depleted and a substantial degradation results.